Cache modules are high-speed memories that facilitate fast retrieval of information including data and instructions. Typically, cache modules are relatively expensive and are characterized by a small size, especially in comparison to higher-level memory modules.
The performance of modern processor-based systems usually depends upon the cache module performances and especially to a relationship between cache hits and cache misses. A cache hit occurs when an information unit that is present in a cache module memory is requested. A cache miss occurs when the requested information unit is not present in the cache module and has to be fetched from another memory that is termed a higher-level memory module.
Various cache module and processor architectures, as well as data retrieval schemes, were developed over the years, to meet increasing performance demands. These architectures included multi-port cache modules, multi-level cache module architecture, super scalar type processors and the like.
The following U.S. patents and U.S. patent applications, all being incorporated herein by reference, provide a brief summary of some state of the art cache modules and data fetch methods: U.S. Pat. No. 4,853,846 of Johnson et al., titled “Bus expander with logic for virtualizing single cache control into dual channels with separate directories and prefetch for different processors”; U.S. patent application 20020069326 of Richardson et al., titled “Pipelines non-blocking level two cache system with inherent transaction collision-avoidance”; U.S. Pat. No. 5,742,790 of Kawasaki titled “Detection circuit for identical and simultaneous access in a parallel processor system with a multi-way multi-port cache”; U.S. Pat. No. 6,081,873 of Hetherington et al., titled “In-line bank conflict detection and resolution in a multi-ported non-blocking cache”; and U.S. Pat. No. 6,272,597 of Fu et al., titled “Dual-ported, pipelined, two level cache system”.
Processors and other information requesting components are capable of requesting information from a cache module and, alternatively or additionally, from another memory module that can be a higher-level memory module. The higher-level memory module can also be a cache memory, another internal memory and even an external memory.
There are various manners to write information into a cache module or a higher-level memory module. Write-through involves writing one or more information units to the cache module and to the higher-level memory module substantially simultaneously.
Some prior art cache modules include multiple lines that in turn are partitioned to segments. Each segment is associated with a validity bit and a dirty bit. A valid bit indicates whether a certain segment includes valid information. The dirty bit indicates if the segment includes valid information that was previously updated but not sent to the higher-level memory module. If a write back policy is implemented only the segments that are associated with an asserted dirty bit are written to the high-level memory module.
Some prior art cache modules perform mandatory fetch operations and speculative fetch operations. The latter are also known as pre-fetch operations. A mandatory fetch operation involves fetching an information unit that caused a cache miss. The speculative fetch operations are aimed to reduce cache miss events, and replace not-valid segments with valid segments.
When applying both speculative fetch operations and write-through policy the high-level memory module can replace an updated segment residing in the cache memory with a non-updated segment. This can cause a coherency problem.
The following U.S. patents and patent applications illustrate various devices and systems for solving coherency problems: U.S. Pat. Nos. 6,574,714, 6,662,275, 6,021,468 and 6,374,330 of Arimilli et al; U.S. Pat. No. 6,868,482 of Mackenthum et al.; U.S. Pat. No. 6,249,520 of Steely et al.; U.S. Pat. No. 5,953,538 of Duncan; U.S. Pat. No. 6,233,656 of; and U.S. Pat. No. 6,848,030 of.
There is a need to provide an efficient method and device for fetching information to a cache module.